NXP官方linux内核编译

上传到ubuntu
修改顶层Makefile
ARCH		?= $(SUBARCH)
CROSS_COMPILE	?= $(CONFIG_CROSS_COMPILE:"%"=%)
改成
ARCH		?= arm
CROSS_COMPILE	?= arm-linux-gnueabihf-

执行以下指令

make clean
make imx_v7_mfg_defconfig
make -j8

添加自己开发版

  • arch/arm/configs的imx_v7_mfg_defconfig文件进行复制改成aa_wyl_defconfig

  • 将aa_wyl_defconfig文件中"CONFIG_ARCH_MULTI_V6=y"注释掉

  • 执行make aa_wyl_defconfig
    

添加设备树文件

cp arch/arm/boot/dts/imx6ul-14x14-evk.dts arch/arm/boot/dts/imx6ull_wyl_defconfig.dts

修改设备树的Makefile

arch/arm/boot/dts/Makefile

找到CONFIG_SOC_IMX6ULL配置添加自己的dtb

dtb-$(CONFIG_SOC_IMX6ULL) += \
	imx6ull_wyl_defconfig.dtb \

自己板子编译

make distclean
make aa_wyl_defconfig
make menuconfig
make all -j8
或者
make zImage all -j8

问题修改

/usr/bin/ld: scripts/dtc/dtc-parser.tab.o  CC      arch/arm/kernel/asm-offsets.s
:(.bss+0x50): multiple definition of `yylloc'; scripts/dtc/dtc-lexer.lex.o:(.bss+0x0): first defined here
collect2: error: ld returned 1 exit status

进入到scripts/dtc/dtc-lexer.l和dtc-lexer.lex.c_shipped

YYLTYPE yylloc;
改成
extern YYLTYPE yylloc;

完成

arch/arm/boot/zImage
arch/arm/boot/dts/imx6ull_wyl_defconfig.dtb

测试

复制zImage和dtb文件到tftp目录

tftp 80800000 zImage
tftp 83000000 imx6ull_wyl_defconfig.dtb
bootz 80800000 - 83000000

CPU主频修改

aa_wyl_defconfig文件中

CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y

第 1 行,配置 ondemand 为默认调频策略。

第 2 行,使能 powersave 策略。

第 3 行,使能 userspace 策略。

第 4 行,使能 interactive 策略。

第 1 行注释掉,然后在 4 行后面添加: CONFIG_CPU_FREQ_GOV_ONDEMAND=y

EMMC改成8数据线

网络驱动修改

在linux中,所有的驱动修改都涉及到设备树,一般改动只会改动设备树文件内容。

源码

pinctrl_spi4: spi4grp {
			fsl,pins = <
				MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
				MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
				MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x70a1
				MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x80000000
			>;
		};

改成

pinctrl_spi4: spi4grp {
			fsl,pins = <
				MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
				MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1  
			>;
		};

源码

spi4 {
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi4>;
		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
		status = "okay";
		gpio-sck = <&gpio5 11 0>;
		gpio-mosi = <&gpio5 10 0>;
		cs-gpios = <&gpio5 7 0>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpio_spi: gpio_spi@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			registers-default = /bits/ 8 <0x57>;
			spi-max-frequency = <100000>;
		};
	};

改成

spi4 {
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi4>;
		status = "okay";
		gpio-sck = <&gpio5 11 0>;
		gpio-mosi = <&gpio5 10 0>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpio_spi: gpio_spi@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			registers-default = /bits/ 8 <0x57>;
			spi-max-frequency = <100000>;
		};
	};

源码

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;
	imx6ul-evk {
		/*省略其他*/


		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
			>;
		};
}